The present disclosure relates to a solid state image pickup apparatus and a method for manufacturing the same, a semiconductor device, and an electronic device and particularly relates to a solid state image pickup apparatus capable of increasing the reliability in a semiconductor chip in which two semiconductor substrates are bonded to each other and a method for manufacturing the same, a semiconductor device, and an electronic device.
A process for manufacturing the semiconductor chip includes a process for forming a plurality of semiconductor chips on a wafer, and then performing dicing of the wafer along a scribe line provided around the semiconductor chips with a blade to singulate the wafer into individual semiconductor chips.
On the scribe line, a wiring layer is not disposed in order not to block the dicing in many cases. In this case, due to the fact that the wiring layer is not present, recessed steps are formed as compared with a region where the wiring layer is present of the semiconductor chip.
In the semiconductor chip manufactured by bonding two semiconductor substrates, the bonded surface has recessed steps, and therefore the recessed step portions form voids in some cases. In the following process, the voids are likely to cause separation between the substrates with the voids as the starting point and also cause contamination of mixing with other metals and the like.
In the semiconductor chip in which two semiconductor substrates are bonded to each other, the bonded surface of the two semiconductor substrates is exposed in the state where the wafer is singulated into a chip after dicing. Therefore, cracks are likely to be formed with the bonded surface as the starting point or moisture absorption occurs with the cracks as the starting point.
On the other hand, JP 2013-62382A, for example, discloses a structure in which even when horizontal cracks are formed with the bonded surface as the starting point, the horizontal cracks are prevented from entering the semiconductor chip by forming grooves at an inner side of the semiconductor chip relative to the dicing line.
Moreover, JP 2010-56319A discloses a structure in which an adhesive with low hardness for bonding substrates to each other is not present on the dicing line. Thus, an interface of materials with greatly different hardness is not present on the dicing line. Therefore, the dicing is stabilized and the occurrence of chipping into the chip is prevented.